Paper
High-Throughput Digital IIR Filter Design
- Authors:
- Zhao Wang; Chiu-Wei Pan; Carl Sechen; Yuanchen Song
- Abstract
- We have implemented a new, very high throughput digital IIR filter architecture that operates at 600 MHz using the IBM 130 nm process at 1.2 V. The inverter fanout-of-four (FO4) delay for the IBM process is 64 ps. The IIR filter’s worst-case stage delay is therefore 26.2 FO4 delays. This is a substantially higher throughput compared to the fastest previously reported IIR filter implementations. The operating frequency was measured using the industry-standard static timing analysis tool (PrimeTime) on a 3D extraction of the complete IIR filter layout. Critical to this achievement is the use of Generalized Carry-Save (GCS) arithmetic, a pipelined IIR filter implementation and a novel implementation of the quantizer. This is the first design that moves the quantizer (limiter) out of the usual final pipeline stage and into its own separate pipeline stage. In previous digital IIR filter designs, the quantizer had to be included in one of the computational stages and hence was a major factor that limited the throughput of the filter. Maximizing the throughput of digital filters is critical today due to the need for low power circuit designs. Even if a lower throughput is desired, first maximizing the throughput and then lowering the power supply voltage to just meet the throughput requirement yields the lowest dynamic energy implementation as the dynamic energy is quadratically related to the supply voltage.
- Keywords
- High Throughput; Digital IIR Filter; GCS Arithmetic; Compressor; Quantizer
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