Paper
Acceleration Study for the FDTD Method Using SSE and AVX Instructions
- Authors:
- Wenhua Yu; Xiaoling Yang; Lihong Zhang
- Abstract
- Parallel Finite Difference Time Domain (FDTD) method has been studied for a long time due to the expensive computation and huge memory needed for its application. In this paper, we introduce a novel hardware acceleration technique based on Vector Arithmetic Logic Unit (VALU) built in a regular CPU for parallel FDTD simulation with Convolutional Perfect Matched Layer (CPML) absorbing boundary condition (ABC). We discuss the acceleration effect for the FDTD method using SSE and AVX instructions and give an implementation on PC. We developed three types of code: code developed by C language, code accelerated by SSE instructions and code accelerated by AVX instructions. We analyse the radiation character of two models of dipole antenna and rectangle micro strip patch antenna using the accelerated code and present the results of a performance study of the FDTD algorithm on Intel 2nd core i5 2320 (quad core) named Sandy Bridge. The results show that we can improve the performance of FDTD algorithm using SSE and AVX instructions.
- Keywords
- FDTD; VALU; SIMD; SSE; AVX; Acceleration
- StartPage
- 101
- EndPage
- 108
- Doi