Paper
Scalable Error Detection Coding© Algorithm for Totally Self-Checking (TSC) Circuits SEDC© Algorithm for TSC Circuits
- Authors:
- Natarajan Somasundaram; Jeong A Lee; Y V Ramana Rao; Ramadass Narayanadass; Farhad Mehdipour
- Abstract
- With continued scaling of silicon process technology, producing reliable electronic components in extremely denser technologies pose a challenge. Further, the systems fabricated in deep sub-micron technology are prone to intermittent or transient faults, causing unidirectional errors, upon exposure to ionizing radiations during system operation. The ability to operate in the intended manner even in the presence of faults is an important objective of all electronic systems. In order to achieve fault-tolerance, each module of the system must be fault-tolerant by possessing run-time (or online) fault detection capabilities. Totally Self-checking (TSC) circuits permit online detection of hardware faults. The Scalable Error Detection Coding (SEDC) algorithm used to design self-checking circuits with faster execution and lesser latency overhead for use in fault-tolerant reconfigurable architecture is presented. SEDC algorithm is formulated and architecture is designed in such a way that for any input binary data length, only area is scaled, with a constant latency of 2 logic gates and requires only a single clock cycle for generating SEDC code. It is shown that the proposed SEDC algorithm is found to be significantly efficient than the existing unidirectional error detection techniques in terms of speed, latency, area and achieving 100% error detection.
- Keywords
- Fault Tolerance; Totally Self-Checking Circuits; Dependable Architecture; Error Detection Coding; Unidirectional Errors
- StartPage
- 116
- EndPage
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