Paper
Synthesizing Neural Nets into Image Processing Hardware
- Authors:
- Michael F. Dossis; Dimitrios E. Amanatidis
- Abstract
- An integrated, formal high-Level synthesis (HLS) framework is used in this work for hardware implementation of cellular neural networks, which are used in real time image processing. The Custom Coprocessors Compilation (CCC) HLS behavioral synthesiser generates correct-by-construction register transfer – level (RTL) VHDL hardware models of computation-intensive applications. Thus, time-consuming RTL and gate-level simulations are avoided and verification time is cut down to a fraction of the usual time that takes to achieve the same goal with traditional approaches. Such applications include image processing with cellular neural networks (CNNs). The synthesizer utilizes formal compiler-compiler and logic programming techniques, to transform algorithmic ADA into RTL VHDL or Verilog which are directly implementable into hardware using any available RTL synthesizer. The CNNs were rapidly coded, compiled and verified along with all the necessary testbenches in GNU ADA. The applications targeted here are edge-detection, halftoning and morphological processing, which are used to evaluate the CCC HLS framework. The contribution of this work is hardware implementation of CNNs using the CCC HLS tools to formally, and rapidly develop, verify and prototype advanced image processing applications.
- Keywords
- Image morphological processing; Formal methods; Cellular Neural Networks; High-level Synthesis; VHDL; ADA; High-level verification
- StartPage
- 10
- EndPage
- 17
- Doi