Paper
High Speed and Power Efficient Compression of Partial Products and Vectors
- Authors:
- Chiuwei Pan; Zhao Wang; Carl Sechen
- Abstract
- A high speed and power efficient compression algorithm for an arbitrarily shaped array of partial products and vectors is presented. Since the full-adder cell is a cornerstone for the carry-save adder (CSA) tree, the most power efficient full-adder cells for building CSA trees for a wide range of delays were ascertained. A minimum hard-ware usage algorithm for an arbitrarily shaped array of vectors was developed. Finally, a new delay-based adder-type selection and CSA-tree wiring algorithm is proposed. This new compression network synthesis (CNS) algorithm was tested on several industrial DSP blocks for a variety of process technologies. CNS produces DSP blocks that consume 20-40% less power for the same delay (throughput) compared to other state-of-the-art designs and compared to the leading commercial synthesis tool.
- Keywords
- Partial Product Compression; DSP Networks; Networks of Additions and Multiplications; Accelerators
- StartPage
- 39
- EndPage
- 54
- Doi