Paper
A FPGA-based Sequencer and Data Acquisition Electronics for CCD Detectors Management
- Authors:
- Mauro Focardi; Emanuele Pace; Maurizio Pancrazzi
- Abstract
- This paper reports on the performances and characteristics of the Sequencer and Data Acquisition (SDAQ) electronics board developed at the Section of Astronomy and Space Science of Department of Physics and Astronomy of the University of Florence, a digital system able to control signals generation and data acquisition, mainly designed for new generation of CCD cameras, but also suitable to drive and acquire data from a large variety of solid state detectors. The SDAQ electronics design is in fact able to generate several digital LVDS signals useful for driving and controlling a solid state detector and some ancillary signals needed to perform analog to digital conversion on data and to perform on-fly data processing, like Correlated Double Sampling (CDS) at the same time. The SDAQ is also able to provide digital signals in order to control data acquisition by means of FPGA internally generated FIFOs and externally mounted static RAMs. Even RAMs are directly controlled by means of FPGA-generated digital signals. Thanks to an external clock driver board and an analog to digital conversion and CDS board hosting the needed electronics components driven by SDAQ, it is possible to adapt, convert, and translate digital signal to TTL levels or other standard levels useful to drive detectors (e.g. CCDs analog phases or CMOS digital signals) and develop a stand-alone electronics system like a camera controller with some useful characteristics. Our electronics is in fact light, compact, and versatile as we were even able to drive a readout circuit developed to read very small currents (of the order of nA or hundreds of pA) generated by EUV-light driven photoelectric effect on Chemical Vapour Deposition (CVD) diamond film detector owning to its versatility. With smart logic residing internally the SDAQ FPGA is based on several finite states machines written in VHDL language (VHSIC Hardware Description Language, where VHSIC means Very-High-Speed Integrated Circuits) and able to efficiently inter-communicate thanks to internal signals and logical ports. The VHDL code hosts several test benches in order to perform by itself some HW and SW checking on the overall SDAQ board, requiring a minimized external circuitry. By this way it is quite simple and relatively fast to perform tests even when the SDAQ is operative (e.g. when it is working inside a CCD camera controller mounted on a ground-based telescope facility). SDAQ’s finite state machines are controlled by means of a FPGA-hosted decoder that is able to decode formatted command coming from the “outside world”. Hereafter we will describe the characteristics of the SDAQ controller as well as the tests and the engineering management procedures performed by means of ours electronics facilities.
- Keywords
- FPGAs; CCD Detectors; Data Processing and Acquisition Electronics; Microcontrollers; RAM memories
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